1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a static random access memory device of which the degree of integration is improved.
2. Description of the Related Art
In general, a static random access memory (SRAM) has a low integration density as compared to a dynamic random access memory (DRAM). However, the SRAM has been used widely in a mid- to small-sized computer due to its high operating speed. An SRAM cell is constituted of a flip-flop circuit including two access transistors, two driver transistors and two load elements. Stored information is maintained as a voltage due to a charge accumulated at a node of the cell. The charge is always supplemented through a load element, so that the SRAM does not require a refresh function in contrast to the DRAM.
The SRAM cell may use a depletion type NMOS transistor as a load element, however, the depletion type NMOS transistor is not used today due to its high power consumption. Instead of the NMOS transistor, a polysilicon resistor having high resistance is widely used such that the power consumption is reduced, simplifying the manufacturing process. However, as the integration density of a memory increases, a full CMOS type SRAM cell adopting a bulk type PMOS transistor as a load element is widely used in order to improve the operation characteristic at low voltage. The full CMOS type SRAM cell has low power consumption in a stand-by mode, and excellent immunity against an .alpha.-particle.
FIG. 1 is a general circuit diagram of an SRAM cell adopting a PMOS transistor as a load element.
Referring to FIG. 1, one SRAM cell includes a pair of inverters which are cross-coupled each other between a power terminal Vcc and ground terminal Vss, and first and second access transistors T1 and T2 of which the sources (or drains) are connected to output nodes of the inverters.
Here, the drain (or source) of the first access transistor T1 and the drain (or source) of the second access transistor T2 are respectively connected to a first bit line BL and a second bit line BL having information opposite to that of the first bit line BL.
Also, a first inverter of the pair of inverters includes a first load transistor T5 constituted of a PMOS transistor and a first driver transistor T3 constituted of an NMOS transistor, and a second inverter of the pair of inverters includes a second load transistor T6 constituted of a PMOS transistor and a second driver transistor T4 constituted of an NMOS transistor.
Also, the first and second access transistors T1 and T2 are both constituted of NMOS transistors, and gate electrodes of the first and second access transistors are connected to word lines WL1 and WL2, respectively.
However, a full CMOS type SRAM cell consists of six transistors, that is, a pair of driver transistors, a pair of access transistors and a pair of load transistor. Thus, it is difficult to realize a high density SRAM with the full CMOS type SRAM cell in spite of its excellent operational characteristics.
When using a bulk type PMOS transistor as a load element of the memory cell, a P-well for forming NMOS driver transistors and NMOS access transistors, and an N-well for forming PMOS load transistors should be formed in the memory cell. Thus, ground voltage and power voltage should be applied to the P-well and the N-well, respectively.
According to the conventional art, after a cell array having a predetermined density is constructed, well pick-up regions for applying bias voltages to the P-well and the N-well should be formed in the other region excluding the cell array. Thus, the chip size is increased by the extra regions (well pick-up regions).